Experience 2021-08 – Present System Analyst, Bosch Global Software Technologies, India Project 1: DASy Vehicle Computer (Driver Assistance System Domain Controller) Is a key component with high bandwidth, computing power and memory. Meeting high security and safety requirements, it collects and merges several technologies (such as radar, video, lidar, ultrasound and highly complex functional algorithms) for a very precise 360° environment model and calculates highly complex functional algorithms for a safe and dynamic vehicle behavior - even at higher speeds. The controller has a small size and a moderate power dissipation. The SOC used for this Vehicle Computer was Texas Instrument’s Jacinto J721e, Which has a Dual Cortex A72, 3 Dual Cortex R5, Dedicated GPU, DSPs and ISPs.
• Involved in the Bootloader Design and implementation for the RTOS and QNX.
• Involved in the Board Bring up Activities, which involved Bring up of RTOS on All the R5 Cores and QNX on the A72 core.
• Different Flashing technique bring up for the SOC like T32, UART, CCS, MMSD and OSPI flashing
• Bring up and Testing of CAN drivers.
• Implementation of the Serial Bootloader which downloads the Images through TFTP for manufacturing Testing.
• Bring up of the Sample Application Ethernet on the MCU Domain(Cortex R5), which involved the ETH firmware for the Switch present on the SOC and programming of the PHY.
• Implementation of the IPC through Shared memory Concept between all the Cores For Data Exchange and Synchronizations. 2019-02 - 2021-08 Senior Software Engineer/Research Engineer, LG Soft, India
Project 1: MPC5.5 (Multi-purpose camera for ADAS) This system is the ADAS Advanced Driver Assistance System front mono camera detecting lanes, traffic signs, lights, and objects (OD) and helping the driver to drive. This ECU was developed on the Renesas Tricore platform, Renesas V3H. We were working mainly on the VP(Vehicle Processor) which runs on the cortex R7 core and its main purpose is to provide system services for the AP(Application processor) which runs on the A53 core.
• Implementation of the WDG, both Internal and External (SBC) using Autosar WDG stack from starch.
• Implemented SWC like Run Time measurement for Runnable and Tasks.
• Implementation of MPU (Memory Protection Unit) for Cortex R7 using Autosar OS for functional safety purpose.
• Involved in the implementation of the SBC wakeup and Sleep process for the V3H.
• Implemented Crash data storing mechanism to save data immediately through FLS driver by avoiding the overhead of FEE and NVM concept.
• Configuration of different drivers like GPT, SPI, I2C, WDG, PWM, PORT and FLS.
• Configuration of BswM for the overall ECU sleep and wake up process and also for SWCs.
• IoHwAb Layer configuration and implementation for communication between SWC and Drivers.
• Involved in solving of critical issues related to Sleep Wake issue, WDG reset Issues, Stack Overflow issues etc.
• Enhancement of SADR SWC component, which is a Data Record in the MercedesBenz vehicles to store necessary information when there is a unexpected events.
• Implementation of Hardware level Functional safety as per Renesas Tricore Architecture o OS System Timer & WDG refresh Timer Monitoring Implementation. o Application and BSW module Runnable Execution monitoring using Autosar WDG stack o MAX20011 DCDC rectifier IC functional Safety Implementation o PWM output monitoring for windshield heater using Loopback through ICU (Input Capture Unit). o NXP FS85 SBC chip functional Safety Implementation. o Unintended Interrupt Handling. Project 2: CAN Stack Development for Slave MCU. This is an internal LGE project for Development of COM stack for NXP MPC5777CRM. This is a bare metal platform where we had to develop all the required drivers and initial setup for slave MCU.
• Involved in the Hardware Bring up.
• Implementing of System and GPT timer drivers.
• Basic UART driver development.
• CAN driver Development as per Autosar Standard with Minimal Functionalities required for Slave MCU
• Development of CanIf, PDUR and CanTp Module with basic configuration support. 2016-08 – 2019-01 Senior Software Engineer, KPIT technologies, India Project 1: AUTOSAR RTE Development (Run Time Environment) The Run-Time Environment (RTE) is at the heart of the AUTOSAR ECU architecture. The RTE is the realization (for an ECU) of the interfaces of the AUTOSAR Virtual Function Bus (VFB). KPIT has their own RTE Code Generator which can be used for Configuration of RTE and Code Generation.
• Involved in designing and implementation of Sender Receiver Implicit and Explicit Communication along with features.
• Embedded template Design development as per Autosar Specification and Implementation of NVBlockSwComponent, Per Instance Memory for Autosar 4.2 and 4.3.
• Involved in designing and implementation of Transformers such SomeIpXf and ComXf. • Development of ECUC rules for RTE module using C4K tool.