OnBenchMark Logo


Software Engineer
Location Pune
Total Views30
back in time
Member since30+ Days ago
 back in time
Contact Details
phone call {{contact.cdata.phone}}
phone call {{contact.cdata.email}}
Candidate Information
  • User Experience
    Experience 1 Year
  • Cost
    Hourly Rate$5
  • availability
  • work from
    Work FromOffsite
  • check list
    CategoryInformation Technology & Services
  • back in time
    Last Active OnMay 07, 2024
Key Skills

Academic Projects Electronic drawing board : Project aim is to develop an electronic system to draw and save pictures by use of ATMEGA328P interfaced with an optical mouse. Output of the optical sensor IC inside the PS/2 mouse varies according to marker movements. Transmitter code is processed by the arduino uno to detect the variation in x coordinate and y coordinates. At the receiver end, xbee receiver receives those symbols from transmitter end. TPG: Done a Test Pattern Generator and implemented in Basys 3 Artix-7 FPGA board. TPG is one of the basic block of BIST circuit to be tested in which data analyzing and compressing has been tested. To reduce power and to avoid unnecessary signal change at the key in active clock pulse, the gray code result is connected to decoder circuit. At this point decoder result is connected to adder through two registers and another register is utilized to store the process result. Binary Counter Based Gated Clock Tree for Integrated CPU Chip: The conventional clock tree, made of some buffers, is prone to large current with the increase in switching clock frequency. The current peak also gets increased when numerous signals, driven by the neighboring sources, switch simultaneously. To eliminate the above stated issue, we have come up with a new approach of designing clock tree consisting of a binary counter and an enable signal generator with reset logic. This work of Binary Counter based Gated Clock Tree Circuit (GCTC) is simulated for 90nm CMOS technology using CADENCE Virtuoso platform at a power supply of 1.2Volt and 5 GHz operating frequency. Traffic Light Controller: Implemented a traffic signal controller in Basys 3 Artix-7 FPGA. Dynamic Obfuscation: Completed PG project on dynamic obfuscation in hardware security to hide the functionality of a circuit to prevent piracy, counterfeiting and illegal overproduction of a chip and implemented in Artix-7 FPGA board.

Copyright© Cosette Network Private Limited All Rights Reserved
Submit Query
WhatsApp Icon